1. Field of the Invention
The present invention relates to a power-on reset circuit that generates a reset signal when power is turned on and, more particularly, to a power-on reset circuit that generates a reset signal when a supply voltage has reached a certain threshold level.
2. Description of the Related Art
A power-on reset circuit as shown in FIG. 1 has been proposed as a type of the power-on reset circuit mentioned above.
Referring to FIG. 1, a resistor R1 and a capacitor C1 are connected to each other in series between Vcc power and ground. A node N1, a common connection point between the resistor R1 and the capacitor C1, is connected to an input terminal of an inverter 1. The inverter 1 is composed of a p-channel MOS (Metal Oxide Semiconductor) transistor Q1 and an n-channel MOS transistor Q2, both of which are connected to each other in series between power-supply voltage Vcc and ground, gates of the transistors Q1, Q2 being commonly connected to each other. In the inverter 1, a gate common connection point between the MOS transistors Q1 and Q2 provides an input terminal, which is connected to the node N1, while a node N2, which is a drain common connection point between the transistors, provides an output terminal from which a reset signal is outputted.
An operation of a power-on reset circuit of related art having the above-mentioned constitution will be described.
First, when the Vcc power is turned on, the power-supply voltage Vcc goes up. When a potential difference relative to the node N1 has exceeded a threshold voltage of the p-channel MOS transistor Q1, the MOS transistor Q1 is turned on. In the initial stage of this power-on operation, a charging voltage of the capacitor C1 remains low.
When the p-channel MOS transistor Q1 is turned on, a potential of the node N2 goes high, outputting a reset signal. Then, as time passes, the charging voltage of the capacitor C1 increases and when the potential of the node N1 exceeds a threshold voltage of the n-channel MOS transistor Q2, the MOS channel transistor Q2 is turned on. This causes the potential of the node N2 to go low, thereby preventing the reset signal from being outputted.
However, in a power-on reset circuit of the related art having the above-mentioned constitution, when the power voltage Vcc is quickly raised, the reset signal is stably generated by the above-mentioned circuit operation; when the power voltage Vcc is very slowly raised, the potential of the node N1 exceeds the threshold voltage of the n-channel MOS transistor Q2 before the potential difference between the power-supply voltage Vcc and the node N1 exceeds the threshold voltage of the p-channel MOS transistor Q1, thereby failing to generate the reset signal.